The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2024

Filed:

Jun. 01, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gregg William Baeckler, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/337 (2020.01); G06F 30/34 (2020.01); G06F 30/373 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/58 (2006.01); H01L 25/03 (2006.01); G06F 111/16 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/337 (2020.01); G06F 30/373 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2111/16 (2020.01); H01L 23/48 (2013.01); H01L 23/52 (2013.01); H01L 23/58 (2013.01); H01L 25/03 (2013.01);
Abstract

A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.


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