The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2024
Filed:
Mar. 24, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Chunhui Mei, San Diego, CA (US);
Hong Jiang, El Dorado Hills, CA (US);
Jiasheng Chen, El Dorado Hills, CA (US);
Yongsheng Liu, San Diego, CA (US);
Yan Li, San Diego, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 15/80 (2006.01); G06F 17/11 (2006.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/30043 (2013.01); G06F 15/8046 (2013.01); G06F 17/11 (2013.01);
Abstract
Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.