The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

May. 29, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Hsueh-Chun Hsiao, Hsinchu County, TW;

Yi-Ning Peng, Miaoli County, TW;

Tzu-Yun Chang, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/30 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66492 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/7833 (2013.01); H01L 29/7881 (2013.01);
Abstract

An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.


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