The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Dec. 23, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stanislav Gens, Nazareth Illit, IL;

Roi Fridburg, Haifa, IL;

Preston Hunt, Portland, OR (US);

Ido Ouzieli, Tel aviv, IL;

Emily Qi, Gig Harbor, WA (US);

Ehud Reshef, Qiryat Tivon, IL;

Izoslav Tchigevsky, Haifa, IL;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04W 12/06 (2021.01); H04L 5/00 (2006.01); H04W 12/037 (2021.01); H04W 76/10 (2018.01); H04W 76/30 (2018.01); H04W 84/12 (2009.01); H04W 88/08 (2009.01);
U.S. Cl.
CPC ...
H04W 12/068 (2021.01); H04L 5/0048 (2013.01); H04W 12/037 (2021.01); H04W 76/10 (2018.02); H04W 76/30 (2018.02); H04W 84/12 (2013.01); H04W 88/08 (2013.01);
Abstract

Provided herein are apparatus and methods for Wi-Fi network profile verification. An apparatus for a wireless communication device includes: a memory; and processor circuitry coupled with the memory, wherein the processor circuitry is to: encode a verification sequence in a probe request for transmission to an AP; decode, in response to the probe request, a probe response received from the AP to obtain a first verification result; determine a second verification result based on the verification sequence and a verification password (VP) obtained from the AP; and determine whether a verification for the AP is successful or not based on the first verification result and the second verification result, and wherein the memory is to store the VP. Other embodiments may also be disclosed and claimed.


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