The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2024
Filed:
Sep. 22, 2021
Applicant:
Infineon Technologies Austria Ag, Villach, AT;
Inventors:
Oliver Blank, Villach, AT;
Heimo Hofer, Bodensdorf, AT;
Andreas Kleinbichler, Villach, AT;
Martin Poelzl, Ossiach, AT;
Assignee:
Infineon Technologies Austria AG, Villach, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/3065 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 21/28123 (2013.01); H01L 21/3065 (2013.01); H01L 29/4925 (2013.01); H01L 29/66712 (2013.01); H01L 29/7813 (2013.01); H01L 29/0865 (2013.01); H01L 29/41766 (2013.01);
Abstract
A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described.