The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2024
Filed:
Jan. 26, 2022
Applicant:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Inventors:
Hung-Yao Huang, Hsinchu County, TW;
Shyng-Yeuan Che, Hsinchu County, TW;
Ching-Hsiu Wu, Hsinchu, TW;
Assignee:
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/76804 (2013.01); H01L 21/76843 (2013.01); H01L 21/76883 (2013.01);
Abstract
A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.