The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2024

Filed:

Oct. 10, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Pankaj Sharma, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); G06F 3/01 (2006.01); G06F 3/0481 (2022.01); G06F 3/04817 (2022.01); G06F 3/0482 (2013.01); G06F 3/0484 (2022.01); G06F 3/04883 (2022.01); G06F 3/04886 (2022.01); G06Q 10/10 (2023.01); G11B 27/10 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H04L 65/403 (2022.01); H04N 21/00 (2011.01); H04N 21/472 (2011.01); H04N 21/84 (2011.01); H04N 21/854 (2011.01);
U.S. Cl.
CPC ...
G06F 3/0416 (2013.01); G06F 3/0481 (2013.01); G06F 3/04817 (2013.01); G06F 3/0482 (2013.01); G06F 3/0484 (2013.01); G06F 3/04883 (2013.01); G06F 3/04886 (2013.01); G06Q 10/10 (2013.01); H01L 29/24 (2013.01); H01L 29/42324 (2013.01); H01L 29/7827 (2013.01); H01L 29/78391 (2014.09); H01L 29/7889 (2013.01); H04L 65/403 (2013.01); H04N 21/47205 (2013.01); H04N 21/854 (2013.01); G06F 3/01 (2013.01); G06F 2203/04105 (2013.01); G06F 2203/04803 (2013.01); G06F 2203/04808 (2013.01); G11B 27/10 (2013.01); H04N 21/00 (2013.01); H04N 21/84 (2013.01);
Abstract

Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.


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