The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2024
Filed:
Jul. 23, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Tejas Nagendra Babu Nama, Sunnyvale, CA (US);
Ruddhi Chaphekar, Santa Clara, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Raghu Prabhakar, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Junjue Wang, San Mateo, CA (US);
Kaizhao Liang, Palo Alto, CA (US);
Adi Fuchs, West Windsor, NJ (US);
Matheen Musaddiq, Austin, TX (US);
Arvind Krishna Sujeeth, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is a data processing system that includes a plurality of reconfigurable processors and processor memory. Runtime logic, operatively coupled to the plurality of reconfigurable processors and the processor memory, is configured to configure at least one reconfigurable processor in the plurality of reconfigurable processors with a first subgraph in a sequence of subgraphs of a graph; load an input onto the processor memory; on a tile-by-tile basis, process a first set of input tiles from the input through the first subgraph and generate a first set of intermediate tiles, load the first set of intermediate tiles onto the processor memory, and process the first set of intermediate tiles through the first subgraph and generate a first set of output tiles; and compose output tiles in the first set of output tiles into a first composed input, and load the first composed input onto the processor memory.