The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Jul. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ching-Kai Shen, Hsinchu County, TW;

Yi-Chuan Teng, Hsinchu County, TW;

Wei-Chu Lin, Hsinchu, TW;

Hung-Wei Liang, New Taipei, TW;

Jung-Kuo Tu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53295 (2013.01); H01L 21/76898 (2013.01); H01L 23/3171 (2013.01); H01L 23/34 (2013.01); H01L 23/481 (2013.01);
Abstract

A method for forming a semiconductor device includes receiving a first bonded to a second substrate by a dielectric layer, wherein a conductive layer is disposed in the dielectric layer and a cavity is formed between the first substrate, the second substrate and the dielectric layer; forming a via opening in the second substrate to expose the conductive layer and a vent hole in the substrate to couple to the cavity; forming a first buffer layer covering sidewalls of the via opening and a second buffer layer covering sidewalls of the vent hole; and forming a connecting structure in the via opening and a sealing structure to seal the vent hole.


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