The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Feb. 27, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masanobu Shirakawa, Chigasaki, JP;

Tsukasa Tokutomi, Kamakura, JP;

Marie Takada, Yokohama, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.


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