The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Feb. 02, 2017
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics International N.v., Amsterdam, NL;

Inventors:

Thomas Boesch, Rovio, CH;

Giuseppe Desoli, San Fermo Della Battaglia, IT;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2006.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/347 (2020.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/0464 (2023.01); G06N 3/047 (2023.01); G06N 3/084 (2023.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01); G06F 9/445 (2018.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01); G06F 115/02 (2020.01); G06F 115/08 (2020.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01); G06N 7/01 (2023.01);
U.S. Cl.
CPC ...
G06N 3/0464 (2023.01); G06F 30/327 (2020.01); G06F 30/34 (2020.01); G06F 30/347 (2020.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/047 (2023.01); G06N 3/084 (2013.01); G06N 20/00 (2019.01); G06N 20/10 (2019.01); G06F 9/44505 (2013.01); G06F 13/4022 (2013.01); G06F 15/7817 (2013.01); G06F 2115/02 (2020.01); G06F 2115/08 (2020.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 7/01 (2023.01);
Abstract

Embodiments are directed towards a hardware accelerator engine that supports efficient mapping of convolutional stages of deep neural network algorithms. The hardware accelerator engine includes a plurality of convolution accelerators, and each one of the plurality of convolution accelerators includes a kernel buffer, a feature line buffer, and a plurality of multiply-accumulate (MAC) units. The MAC units are arranged to multiply and accumulate data received from both the kernel buffer and the feature line buffer. The hardware accelerator engine also includes at least one input bus coupled to an output bus port of a stream switch, at least one output bus coupled to an input bus port of the stream switch, or at least one input bus and at least one output bus hard wired to respective output bus and input bus ports of the stream switch.


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