The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2024
Filed:
Dec. 22, 2020
Intel Corporation, Santa Clara, CA (US);
Noor Mubeen, Bangalore, IN;
Ashraf H. Wadaa, Beaverton, OR (US);
Andrey Gabdulin, Ramat-Gan, IL;
Russell Fenger, Beaverton, OR (US);
Deepak Samuel Kirubakaran, Hillsboro, OR (US);
Marc Torrant, Folsom, CA (US);
Ryan Thompson, Beaverton, OR (US);
Georgina Saborio Dobles, Pavas, CR;
Lingjing Zeng, Shanghai, CN;
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest Vfor energy-efficiency. Such Vvalues may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V. A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V. Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.