The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2024

Filed:

Jun. 28, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Kinney, Coopersburg, PA (US);

Zoran Zivkovic, Hertogenbosch, NL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 15/80 (2013.01); G06F 1/12 (2013.01);
Abstract

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture implements a data driven synchronization process to maintain synchronization between the programmable elements (PEs) of the programmable processing array. The hybrid architecture implements a timer-based solution to ensure data-driven synchronization between the PEs of the programmable processing array meets the time-based synchronization requirements of the overall system. The timers function to introduce a delay or latency to the time required by each of the PEs of the programmable processing array to perform their respective tasks, thereby forcing the hardware blocks to wait to receive the processed data samples output via the PEs and perform their hardware-based computations.


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