The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Apr. 15, 2022
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Jorge Vasquez, San Jose, CA (US);
Bartlomiej Adam Kardasz, Pleasanton, CA (US);
Jacob Anthony Hernandez, Morgan Hill, CA (US);
Thomas D. Boone, San Carlos, CA (US);
Georg Wolf, San Francisco, CA (US);
Mustafa Pinarbasi, Morgan Hill, CA (US);
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Abstract
A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.