The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2024

Filed:

Nov. 12, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yoshiaki Fukuzumi, Yokkaichi Mie, JP;

Keisuke Suda, Yokkaichi Mie, JP;

Fumiki Aiso, Kuwana Mie, JP;

Atsushi Fukumoto, Mie Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); G11C 5/06 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); H10B 43/27 (2023.02);
Abstract

A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.


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