The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Mar. 30, 2018
International Business Machines Corporation, Armonk, NY (US);
Rathinakumar Appuswamy, San Jose, CA (US);
John V. Arthur, Mountain View, CA (US);
Andrew S. Cassidy, San Jose, CA (US);
Pallab Datta, San Jose, CA (US);
Steven K. Esser, San Jose, CA (US);
Myron D. Flickner, San Jose, CA (US);
Jennifer Klamo, San Jose, CA (US);
Dharmendra S. Modha, San Jose, CA (US);
Hartmut Penner, San Jose, CA (US);
Jun Sawada, Austin, TX (US);
Brian Taba, Cupertino, CA (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Defect resistant designs for location-sensitive neural network processor arrays are provided. In various embodiments, plurality of neural network processor cores are arrayed in a grid. The grid has a plurality of rows and a plurality of columns. A network interconnects at least those of the plurality of neural network processor cores that are adjacent within the grid. The network is adapted to bypass a defective core of the plurality of neural network processor cores by providing a connection between two non-adjacent rows or columns of the grid, and transparently routing messages between the two non-adjacent rows or columns, past the defective core.