The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2024
Filed:
Apr. 03, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Frederick A. Ware, Los Altos Hills, CA (US);
Kenneth L. Wright, Sunnyvale, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1684 (2013.01); G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/0784 (2013.01); G06F 11/079 (2013.01); G06F 11/1044 (2013.01); G06F 11/1048 (2013.01); G06F 11/1658 (2013.01); G06F 11/2007 (2013.01); G06F 13/4027 (2013.01); Y02D 10/00 (2018.01);
Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.