The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Apr. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventors:

Shun-Neng Wang, New Taipei, TW;

Tung-Huang Chen, Taichung, TW;

Ching-Hung Kao, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/10 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H10B 41/10 (2023.02); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01);
Abstract

A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.


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