The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Jul. 31, 2020
Applicant:

Hitachi Energy Ltd, Zürich, CH;

Inventors:

Marco Bellini, Schlieren, CH;

Lars Knoll, Hägglingen, CH;

Stephan Wirths, Thalwil, CH;

Assignee:

Hitachi Energy Ltd, Zürich, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/04 (2006.01); H01L 29/16 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/0485 (2013.01); H01L 29/41775 (2013.01); H01L 29/42376 (2013.01); H01L 29/66068 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01);
Abstract

A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.


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