The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2024
Filed:
Aug. 12, 2021
Changxin Memory Technologies, Inc., Anhui, CN;
ChihCheng Liu, Hefei, CN;
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
Abstract
A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes following operations. A semiconductor substrate is provided. The semiconductor substrate includes an array region and a peripheral region, a plurality of conductive layers are arranged in array region and separated from each other. A support layer covering the semiconductor substrate is formed. An interconnect layer is arranged in support layer located on the array region and extends to peripheral region. The interconnect layer is electrically connected to a respective one of the conductive layers and transmits an electrical signal of the respective one of the conductive layers to the peripheral region. The support layer is patterned to form a plurality of support structures located on the peripheral region and separated from each other and an interconnect structure located on the array region and peripheral region. The interconnect layer is located in the interconnect structure.