The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2024

Filed:

Mar. 16, 2022
Applicants:

Stmicroelectronics Application Gmbh, Aschheim-Dornach, DE;

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Roberto Colombo, Munich, DE;

Vivek Mohan Sharma, New Delhi, IN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/07 (2006.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2273 (2013.01); G06F 11/0772 (2013.01); G06F 11/079 (2013.01); G06F 11/2733 (2013.01);
Abstract

A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.


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