The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Apr. 27, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Mohammad Sadegh Jalali, Toronto, CA;

Marcus Van Ierssel, Toronto, CA;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03267 (2013.01); H04L 25/03057 (2013.01); H04L 25/03146 (2013.01);
Abstract

A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.


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