The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

Aug. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jerrin Pathrose Vareed, Hsinchu, TW;

Shiba Mohanty, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/037 (2013.01);
Abstract

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.


Find Patent Forward Citations

Pathrose Vareed, Jerrin. (2024). Semiconductor device including a level shifter and method of mitigating a delay between input and output signals (U.S. Patent No. 12057832). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12057832

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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