The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2024
Filed:
Jan. 03, 2022
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Patrick Morrow, Portland, OR (US);
Rishabh Mehandru, Portland, OR (US);
Aaron D. Lilak, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/8221 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01); H01L 21/823475 (2013.01); H01L 27/088 (2013.01); H01L 29/0673 (2013.01);
Abstract
A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.