The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2024

Filed:

May. 04, 2023
Applicant:

Epistar Corporation, Hsinchu, TW;

Inventors:

Min-Hsun Hsieh, Hsinchu, TW;

De-Shan Kuo, Hsinchu, TW;

Chang-Lin Lee, Hsinchu, TW;

Jhih-Yong Yang, Hsinchu, TW;

Assignee:

EPISTAR CORPORATION, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/677 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
H01L 21/67721 (2013.01); H01L 21/67144 (2013.01); H01L 21/67288 (2013.01); H01L 21/6773 (2013.01); H01L 21/6836 (2013.01); H01L 33/0075 (2013.01); H01L 2221/68322 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68368 (2013.01);
Abstract

A chip transferring method includes providing a plurality of chips on a first load-bearing structure; measuring photoelectric characteristic values of the plurality of chips; categorizing the plurality of chips into a first portion chips and a second portion chips according to the photoelectric characteristic values of the plurality of chips, wherein the second portion chips comprise parts of the plurality of chips which photoelectric characteristic value falls within an unqualified range; removing the second portion chips from the first load-bearing structure; dividing the first portion chips into a plurality of blocks according to the photoelectric characteristic values, and each of the plurality of blocks comprising multiple chips of the first portion chips; and transferring the multiple chips of one of the plurality of blocks to a second load-bearing structure.


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