The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2024
Filed:
Feb. 24, 2023
Cadence Design Systems, Inc., San Jose, CA (US);
Sagar Kumar, Rudrapur, IN;
Rajesh Khurana, Noida, IN;
Vivek Chickermane, Slaterville Springs, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods and systems are provided for testing three-dimensional (3D) stacked dies of integrated circuits (ICs). The methods and systems receive, by test signal routing logic implemented on a first die, a first die test signal, the test signal routing logic operating in an elevate mode or turn mode. The methods and systems receive a second die test signal from a second die and route the first die test signal to an external device in the turn mode. The methods and systems route the second die test signal received from the second die to the external device in the elevate mode.