The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2024
Filed:
Aug. 10, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Dmitri E. Nikonov, Beaverton, OR (US);
Clifford Lu Ong, Portland, OR (US);
Ian A. Young, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G06N 3/063 (2023.01); G11C 11/54 (2006.01); H01L 25/065 (2023.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); G06N 3/063 (2013.01); G11C 11/54 (2013.01); H01L 25/0657 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78391 (2014.09); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H01L 2225/06506 (2013.01);
Abstract
Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.