The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2024

Filed:

May. 19, 2022
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventors:

Ashish Darbari, Abbots Langley, GB;

Iain Singleton, Hemel Hempstead, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 30/33 (2020.01); G06F 30/333 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 11/076 (2013.01); G06F 11/3055 (2013.01); G06F 30/33 (2020.01); G06F 30/333 (2020.01);
Abstract

A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.


Find Patent Forward Citations

Loading…