The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2024
Filed:
Jun. 16, 2022
Teradyne, Inc., North Reading, MA (US);
Martin Hollander, Son en Breugel, NL;
Teradyne, Inc., North Reading, MA (US);
Abstract
Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.