The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Aug. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Chien-Hung Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); H01L 21/033 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H01L 21/0337 (2013.01); H01L 29/0649 (2013.01); H01L 29/40117 (2019.08); H01L 29/42352 (2013.01); H10B 43/50 (2023.02);
Abstract

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC has a plurality of logic devices disposed on a logic region of a substrate, including a first logic device configured to operate at a first voltage and comprising a first logic gate electrode separated from the substrate by a first logic gate dielectric. The first logic gate dielectric is disposed along sidewall and bottom surfaces of a logic device trench of the substrate, and the first logic gate electrode is disposed conformally along the first logic gate dielectric within the logic device trench. A hard mask layer is disposed on the first logic gate electrode within the logic device trench.


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