The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Jul. 05, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Szu-Yu Wang, Hsinchu, TW;

Chia-Wei Hu, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42328 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 29/40114 (2019.08); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 21/02532 (2013.01); H01L 21/0262 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for forming a semiconductor structure includes receiving a substrate including a first gate structure; forming a first semiconductor layer over the first gate structure, forming a second semiconductor layer on the first semiconductor layer, performing an etching back operation to remove a portion of the second semiconductor layer and a portion of the first semiconductor layer with an etchant, the etching rate of the first semiconductor layer upon exposure to the etchant is greater than an etching rate of the second semiconductor layer upon exposure to the etchant; forming a hard mask spacer over the first semiconductor layer and the second semiconductor layer, a portion of the second semiconductor layer is exposed through the hard mask spacer; removing the portions of the second semiconductor layer and the first semiconductor layer through the hard mask spacer to form a second gate structure and expose a portion of the substrate.


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