The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Apr. 18, 2024
Applicant:

Southeast University, Nanjing, CN;

Inventors:

Long Zhang, Nanjing, CN;

Weifeng Sun, Nanjing, CN;

Siyang Liu, Nanjing, CN;

Chengwu Pan, Nanjing, CN;

Guiqiang Zheng, Nanjing, CN;

Longxing Shi, Nanjing, CN;

Assignee:

SOUTHEAST UNIVERSITY, Nanjing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 23/528 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/8605 (2006.01); H01L 29/872 (2006.01); H01L 49/02 (2006.01); H02M 1/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0605 (2013.01); H01L 23/5286 (2013.01); H01L 27/0629 (2013.01); H01L 27/0635 (2013.01); H01L 28/60 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01); H01L 29/8605 (2013.01); H01L 29/872 (2013.01); H02M 1/08 (2013.01);
Abstract

In the monolithically integrated GaN-based half-bridge circuit, a nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially provided on a conductive substrate, the barrier layer and the channel layer are separated by isolation layers, and a diode, an integrated capacitor, a low-side transistor, a high-side transistor, a first integrated resistor and a second integrated resistor are provided. The half-bridge circuit includes: a low-side transistor and a high-side transistor, wherein a drain of the low-side transistor is connected to a source of the high-side transistor and also connected to an output terminal Vout, and a substrate of the low-side transistor is connected to a substrate of the high-side transistor, wherein a series resistor is connected in parallel to a drain of the high-side transistor and a source of the low-side transistor.


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