The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Jun. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Naveed Zaman, Saratoga, CA (US);

Aravind Dasu, Milpitas, CA (US);

Sreedhar Ravipalli, Cupertino, CA (US);

Rakesh Cheerla, Cupertino, CA (US);

Martin Horne, Alamo, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H04L 9/40 (2022.01); H04L 47/10 (2022.01); H04L 49/90 (2022.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H04L 47/10 (2013.01); H04L 49/90 (2013.01); H04L 63/1458 (2013.01);
Abstract

A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.


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