The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

May. 28, 2019
Applicant:

Tahoe Research, Ltd., Dublin, IE;

Inventors:

Pete D. Vogt, Boulder, CO (US);

Andre Schaefer, Sasssenburg, DE;

Warren Morrow, Steilacoom, WA (US);

John B. Halbert, Beaverton, OR (US);

Jin Kim, Portland, OR (US);

Kenneth D. Shoemaker, Los Altos Hills, CA (US);

Assignee:

Tahoe Research, Ltd., Dublin, IE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 5/06 (2013.01); H01L 23/481 (2013.01); H10B 12/00 (2023.02); H10B 12/50 (2023.02); H01L 24/16 (2013.01); H01L 2224/16146 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H10B 12/48 (2023.02);
Abstract

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.


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