The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Mar. 11, 2022
Applicant:

Shanghai Huali Integrated Circuit Corporation, Shanghai, CN;

Inventor:

Yong Li, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823821 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 29/66795 (2013.01); H01L 21/0228 (2013.01); H01L 29/7848 (2013.01);
Abstract

The present application discloses a method for manufacturing a fin field effect transistor, comprising: step: forming fins; step, forming first gate structures; and step, forming source and drain areas, comprising: step: forming a second hard mask layer; step: opening a formation area of FinFET, and performing the first time etching on the second hard mask layer; step: performing the second time etching to form first grooves in the fins, wherein the second time etching vertically and horizontally etches the isolation dielectric layer, when the second groove is formed next to the exposed surfaces of the isolation dielectric layer, the exposed surfaces of the fins and the first polysilicon gate, as the result, the second groove forms a bridge path; step: forming a sacrificial sidewall to fully fill the bridge path; and step: filling the first groove with an epitaxial layer.


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