The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Jan. 02, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Elias Lee Fallon, Allison Park, PA (US);
David Allan White, San Jose, CA (US);
Regis R Colwell, Gibsonia, PA (US);
Hongzhou Liu, Sewickley, PA (US);
Hui Xu, Wexford, PA (US);
Wangyang Zhang, Allison Park, PA (US);
Shang Li, Greenbelt, MD (US);
Hua Luo, Pittsburgh, PA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for genetic placement of analog and mix-signal circuit components. Embodiments may include receiving an unplaced layout associated with an electronic circuit design and grouping requirements. Embodiments may also include identifying one or more instances that need to be placed in the unplaced layout and areas of the unplaced layout configured to receive the instances. Embodiments may further include analyzing one or more instances that need to be placed in the unplaced layout and the areas of the unplaced layout configured to receive the instances, wherein analyzing is based upon a row-based data structure. Embodiments may also include determining a location and an orientation for each of the one or more instances based upon the genetic algorithm and generating a placed layout based upon the determined location and orientation for each of the instances.