The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Aug. 11, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Wei Lin, Taipei, TW;

Chang-Ming Wu, New Taipei, TW;

Ting-Jung Chen, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 31/00 (2006.01); B81B 1/00 (2006.01); B81B 3/00 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81B 3/001 (2013.01); B81B 1/004 (2013.01); B81B 3/0021 (2013.01); B81C 1/00158 (2013.01); B81C 1/00531 (2013.01); B81C 1/00571 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/053 (2013.01);
Abstract

The present disclosure provides a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.


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