The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Mar. 14, 2024
Applicant:

Monolithic 3d Inc., Klamath Falls, OR (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Jin-Woo Han, San Jose, CA (US);

Eli Lusky, Ramat-Gan, IL;

Assignee:

Monolithic 3D Inc., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); G11C 16/28 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 51/20 (2023.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); G11C 16/28 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 51/20 (2023.02); G11C 16/14 (2013.01); H01L 2224/08145 (2013.01);
Abstract

A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.


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