The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Sep. 28, 2021
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventor:

Roberto Tiziani, Nerviano, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01); H01L 23/488 (2006.01); H01L 23/495 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 23/15 (2013.01); H01L 23/3107 (2013.01); H01L 23/488 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 23/49838 (2013.01); H01L 23/49872 (2013.01); H01L 23/522 (2013.01); H01L 23/5389 (2013.01); H01L 24/45 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 2224/4824 (2013.01); H01L 2924/181 (2013.01);
Abstract

A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.


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