The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Oct. 25, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Francesc Guim Bernat, Barcelona, ES;

Da-Ming Chiang, San Jose, CA (US);

Kshitij A. Doshi, Tempe, AZ (US);

Suraj Prabhakaran, Aachen, DE;

Mark A. Schmisseur, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 9/455 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 13/362 (2006.01); G06F 13/42 (2006.01); G06N 3/02 (2006.01); G06N 3/04 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 9/45533 (2013.01); G06F 9/5027 (2013.01); G06F 9/54 (2013.01); G06F 13/362 (2013.01); G06F 13/4265 (2013.01); G06F 13/4282 (2013.01); G06N 3/02 (2013.01); G06N 3/04 (2013.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06F 2213/0026 (2013.01);
Abstract

There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.


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