The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2024
Filed:
Jun. 14, 2022
Intel Corporation, Santa Clara, CA (US);
Renu Patle, Folsom, CA (US);
Hanmanthrao Patli, Folsom, CA (US);
Rakesh Mehta, San Jose, CA (US);
Hagay Spector, Sderot, IL;
Ivan Herrera Mejia, El Dorado Hills, CA (US);
Fylur Rahman Sathakathulla, Folsom, CA (US);
Gowtham Raj Karnam, Folsom, CA (US);
Mohsin Ali, San Jose, CA (US);
Sahar Sharabi, Beer Yaakov, IL;
Abraham Halevi Fraenkel, Jerusalem, IL;
Eyal Pniel, Susya, IL;
Ehud Cohn, Bruchin, IL;
Raghav Ramesh Lakshmi, Folsom, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.