The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jan. 15, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Li Chiang, Taipei, TW;

Jer-Fu Wang, Taipei, TW;

Chao-Ching Cheng, Hsinchu, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Chih-Chieh Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1157 (2017.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/792 (2006.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/66833 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 29/792 (2013.01);
Abstract

A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.


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