The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Nov. 28, 2023
Applicant:

Cellink Corporation, San Carlos, CA (US);

Inventors:

Kevin Michael Coakley, Belmont, CA (US);

Malcolm Parker Brown, Mountain View, CA (US);

Dongao Yang, Redwood City, CA (US);

Michael Lawrence Miller, San Mateo, CA (US);

Paul Henry Lego, Woodside, CA (US);

Assignee:

CelLink Corporation, San Carlos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H01M 50/519 (2021.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/06 (2006.01); H05K 3/20 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0201 (2013.01); H01M 50/519 (2021.01); H05K 1/118 (2013.01); H05K 3/007 (2013.01); H05K 3/0073 (2013.01); H05K 3/06 (2013.01); H05K 3/20 (2013.01); H05K 3/281 (2013.01); H05K 3/4623 (2013.01); H05K 3/064 (2013.01); H05K 2201/0145 (2013.01); H05K 2201/015 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/10037 (2013.01); H05K 2203/066 (2013.01); Y02E 60/10 (2013.01); Y10T 29/49156 (2015.01);
Abstract

A method of forming a flexible interconnect circuit is described. The method may comprise laminating a substrate to a conductive layer and patterning the conductive layer using a laser while the conductive layer remains laminated to the substrate thereby forming a first conductive portion and a second conductive portion of the conductive layer. The substrate maintains the orientation of the first conductive portion relative to the second conductive portion during and after patterning. The method may also comprise laminating a first insulator to the conductive layer and removing the substrate from the conductive layer such that the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion while and after the substrate is removed. The method may also comprise laminating a second insulator to the second side of the conductive layer while the first insulator remains laminated to the substrate.


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