The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Mar. 27, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hayato Oishi, Tokyo, JP;

Satoru Sugimoto, Tokyo, JP;

Hiroki Hosaka, Tokyo, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02372 (2013.01); H01L 2924/1434 (2013.01);
Abstract

Memory devices are disclosed. A memory device may include a first row of power supply pads and a first row of input/output (DQ) pads. The memory device may further include a row of vias, wherein the first row of DQ pads is positioned at least partially between the row of vias and the first row of power supply pads. The memory device may also include a number of conductors, wherein each via of the row of vias is coupled, via an associated conductor of the number of conductors, to either a power supply pad of the first row of power supply pads or a DQ pad of the first row of DQ pads. Methods of forming an interface region of a memory device, and electronic systems are also disclosed.


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