The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Sep. 02, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Xianlei Cao, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/525 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5252 (2013.01); H01L 23/53295 (2013.01);
Abstract

A preparation method of the semiconductor structure includes: providing a substrate including a core device region and an anti-fuse device region; forming a first dielectric layer covering the core device region and the anti-fuse device region; forming a second dielectric layer covering the first dielectric layer and having a dielectric constant larger than a dielectric constant of the first dielectric layer; removing the second dielectric layer on the anti-fuse device region; and forming a conductive layer covering the first dielectric layer on the anti-fuse device region and the second dielectric layer on the core device region.


Find Patent Forward Citations

Cao, Xianlei. (2024). Semiconductor structures of anti-fuse devices and core devices with different dielectric layers and preparation method thereof (U.S. Patent No. 12033938). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12033938

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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