The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2024
Filed:
Mar. 10, 2021
Applicant:
Changxin Memory Technologies, Inc., Hefei, CN;
Inventor:
Kaimin Lv, Hefei, CN;
Assignee:
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4846 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/13553 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/182 (2013.01); H01L 2924/37001 (2013.01);
Abstract
The present disclosure relates to the technical field of semiconductor packaging, and discloses a semiconductor structure and a method for forming the same. The method includes: providing a chip, the chip having interconnect structures on its surface, the top of the interconnect structures having an exposed fusible portion; providing a substrate, the substrate having conductive structures on its surface; patterning the conductive structures so that edges of the conductive structures have protrusions; combining the chip with the substrate.