The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jun. 30, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Biao Cheng, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 29/02 (2006.01); G11C 7/04 (2006.01); G11C 7/22 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 29/028 (2013.01); G11C 7/04 (2013.01); G11C 7/222 (2013.01); G11C 29/023 (2013.01); G11C 29/50012 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A method for adjusting margin, a circuit for adjusting margin, and a memory are provided. The method is applicable for a memory including a plurality of delay sub-circuits. The method includes: determining a voltage parameter and a temperature parameter, obtaining a target delay value by performing calculation on the voltage parameter and the temperature parameter through a preset time margin model; and adjusting a time margin of the memory by controlling working states of the plurality of delay sub-circuits according to the target delay value.


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Cheng, Biao. (2024). Method for adjusting margin, circuit for adjusting margin and memory (U.S. Patent No. 12033685). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12033685

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