Memory with address-selectable data poisoning circuitry, and associated systems, devices, and methods

Abstract

Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.