The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Jun. 13, 2022
Applicant:

Toyota Jidosha Kabushiki Kaisha, Toyota, JP;

Inventors:

Kazuaki Okamoto, Toyota, JP;

Hiroshi Yanagimoto, Miyoshi, JP;

Rentaro Mori, Kasugai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01L 31/0445 (2014.01); H01L 31/0747 (2012.01); H01L 31/20 (2006.01); H05K 3/12 (2006.01); H05K 3/16 (2006.01); H05K 3/20 (2006.01); H05K 3/24 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/388 (2013.01); H05K 3/205 (2013.01); H05K 3/241 (2013.01);
Abstract

Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.


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