The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Dec. 23, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Albert Molina, Novelda, ES;

Kameran Azadet, San Ramon, CA (US);

Martin Clara, Santa Clara, CA (US);

Hundo Shin, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/80 (2006.01);
U.S. Cl.
CPC ...
H03M 1/808 (2013.01);
Abstract

A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.


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